View MAX9152_135829.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2003; Rev 0; 4/01
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch
General Description
The MAX9152 2 x 2 crosspoint switch is designed for applications requiring high speed, low power, and lownoise signal distribution. This device includes two LVDS/LVPECL inputs, two LVDS outputs, and two logic inputs that set the internal connections between differential inputs and outputs. The MAX9152 can be programmed to connect any input to either or both outputs, allowing it to be used in the following configurations: 2 2 crosspoint switch, 2:1 mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexibility makes the MAX9152 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration for communication over extended distances. Ultra-low 120psPK-PK (max) PRBS jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees an 800Mbps data rate and less than 50ps (max) skew between channels. LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS inputs are designed to also accept LVPECL signals directly, and PECL signals with an attenuation network. The LVDS outputs are designed to drive 75 or 100 loads, and feature a selectable differential output resistance to minimize reflections. The MAX9152 is available in 16-pin TSSOP and SO packages, and consumes only 109mW while operating from a single +3.3V supply over the -40C to +85C temperature range. o Pin-Programmable Configuration 2 x 2 Crosspoint Switch 2:1 Mux 1:2 Demux 1:2 Splitter Dual Repeater o Ultra-Low 120psPK-PK (max) Jitter with 800Mbps, PRBS = 223 -1 Data Pattern o Low 50ps (max) Channel-to-Channel Skew o 109mW Power Dissipation o Compatible with ANSI TIA/EIA-644 LVDS Standard o Inputs Accept LVDS/LVPECL Signals o LVDS Output Rated for 75 and 100 Loads o Pin-Programmable Differential Output Resistance o Pin-Compatible Upgrade to DS90CP22 (SO Package) o Available in 16-Pin TSSOP Package (Half the Size of SO)
Features
MAX9152
Ordering Information
PART MAX9152ESE MAX9152EUE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 SO 16 TSSOP
Pin Configuration appears at end of data sheet.
Functional Diagram
OUT0+ OUT0OUT1+ OUT1-
Applications
Cell Phone Base Stations Add/Drop Muxes Digital Crossconnects DSLAMs Network Switches/Routers Protection Switching Loopback Diagnostics Clock/Data Distribution Cable Repeaters
MAX9152
EN0
EN1
SEL0
0
1
0
1
SEL1
IN0+ IN0IN1+ IN1-
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_-, OUT_+, OUT_- to GND .......................-0.3V to +4.0V EN_, SEL_, NC/RSEL to GND.....................-0.3V to (VCC + 0.3V) Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70C) 16-Pin SO (derate 8.7mW/C above +70C)................696mW 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection Human Body Model, IN_+, IN_-, OUT_+, OUT_-........... 7kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75 1%, NC/RSEL = high for RL = 100 1%, differential input voltage |VID| = 0.1V to VCC, input voltage (VIN+, VIN-) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA = -40C to +85C. Typical values at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current NC/RSEL INPUT Input High Voltage Input Low Voltage Input High Current Input Low Current DIFFERENTIAL INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Input Current LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Impedance (Note 2) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Common-Mode Voltage Change in Magnitude of VOS Between Complementary Output States RDIFF VOD NC/RSEL = low or open NC/RSEL = high RL = 75, NC/RSEL = open, Figure 1 RL = 100, NC/RSEL = high, Figure 1 RL = 75, NC/RSEL = open, Figure 1 25 RL = 100, NC/RSEL = high, Figure 1 RL = 75, NC/RSEL = open, Figure 1 RL = 100, NC/RSEL = high, Figure 1 RL = 75, NC/RSEL = open, Figure 1 25 RL = 100, NC/RSEL = high, Figure 1 mV 1.150 1.430 V mV 60 85 280 90 122 382 118 155 470 mV VTH VTL VIN+ = VCC or 0, VIN- = VCC or 0 IIN+, IINV I N + = 3. 6 V o r 0 , V I N - = 3 . 6 V or 0 , V CC = 0 -100 -1 -1 1 1 A 100 mV mV VIH VIL IIH IIL VIN = VCC or 2.0V VIN = 0 or 0.8V 2.0 GND 0 -10 VCC 0.8 20 10 V V A A SYMBOL VIH VIL IIH IIL VIN = VCC or 2.0V VIN = 0 or 0.8V CONDITIONS MIN 2.0 GND 0 -10 TYP MAX VCC 0.8 20 10 UNITS V V A A LVCMOS/LVTTL INPUTS (EN_, SEL_)
VOD
VOS
VOS
2
_______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75 1%, NC/RSEL = high for RL = 100 1%, differential input voltage |VID| = 0.1V to VCC, input voltage (VIN+, VIN-) = 0 to VCC, EN_ = high, SEL0 = low, SEL1 = high, and TA = -40C to +85C. Typical values at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS VID = +100mV, VOUT_+ = 0, other output open Output Short-Circuit Current IOS -12 VID = -100mV, VOUT_- = 0, other output open VID = +100mV, VOUT_+ = 0, VOUT_- = 0 VID = -100mV, VOUT_+ = 0, VOUT_- = 0 Disabled, VOUT_+ = VCC or 0, VOUT_- = VCC or 0 VCC = 0, VOUT_+ = 3.6V or 0, VOUT_- = 3.6V or 0 RL = 75, CL = 5pF, enabled, quiescent, Figure 5 RL = 100, CL = 5pF, enabled, quiescent, Figure 5 Supply Current ICC RL = 75, CL = 5pF, enabled, switching at 400MHz (800Mbps), Figure 5 (Note 2) RL = 100, CL = 5pF, enabled, switching at 400MHz (800Mbps), Figure 5 (Note 2) High-Z Supply Current ICCZ Disabled -1 -1 -12 -20 1 1 mA A A -20 mA MIN TYP MAX UNITS
MAX9152
Both Output Short-Circuit Current Output High-Z Current Power-Off Output Current SUPPLY CURRENT
IOSB IOZ+, IOZIOFF+, IOFF-
38 33 58 52 15
55 50 mA 70 65 25 mA
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75 1%, NC/RSEL = high for RL = 100 1%, CL = 5pF, differential input voltage |VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage (VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA = -40C to +85C. Typical values at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Input to SEL Setup Time (Note 5) Input to SEL Hold Time (Note 5) SEL to Switched Output Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Propagation Low-to-High Delay Propagation High-to-Low Delay SYMBOL tSET tHOLD tSWITCH tPHZ tPLZ tPZH tPZL tPLHD tPHLD Figures 2, 3 Figures 2, 3 Figures 2, 3 Figure 4 Figure 4 Figure 4 Figure 4 Figures 5, 6 VCC = +3.3V, TA = +25C; Figures 5, 6 Figures 5, 6 VCC = +3.3V, TA = +25C; Figures 5, 6 1.7 2.0 1.7 2.0 2.3 2.3 2.3 2.3 CONDITIONS MIN 0.4 0.6 1.8 2.5 3.5 3.8 3.8 3.2 3.2 3.4 2.9 3.4 2.9 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
_______________________________________________________________________________________
3
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75 1%, NC/RSEL = high for RL = 100 1%, CL = 5pF, differential input voltage |VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage (VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA = -40C to +85C. Typical values at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Pulse Skew |tPLHD -tPHLD| (Note 6) Output Channel-to-Channel Skew Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (20% to 80%) SYMBOL tSKEW tCCS tLHT tHLT Figures 5, 6 Figures 5, 7 Figures 5, 6 Figures 5, 6 VID = 200mV, VCM = 1.2V, 50% duty cycle, 800Mbps, input transition time = 600ps (20% to 80%) VID = 200mV, VCM = 1.2V, PRBS = 223 - 1 data pattern, 800Mbps, input transition time = 600ps (20% to 80%) 160 160 CONDITIONS MIN TYP 25 20 270 270 MAX 90 50 480 480 UNITS ps ps ps ps
10
30 ps
LVDS Data Path Peak-to-Peak Jitter (Note 7)
tJIT
65
120
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and VOD. Note 2: Guaranteed by design and characterization, not production tested. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: tSET and tHOLD time specify that data must be in a stable state before and after the SEL transition. Note 6: tSKEW is the magnitude difference of differential propagation delay over rated conditions; tSKEW = |tPHLD - tPLHD|. Note 7: Specification includes test equipment jitter.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID = 200mV, PRBS = 223 - 1 data pattern, VCM = +1.2V, TA = +25C, unless otherwise noted.)
DIFFERENTIAL OUTPUT EYE PATTERN IN 1:2 SPLITTER MODE AT 800Mbps
MAX9152 toc01
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9152 toc02
SUPPLY CURRENT vs. DATA RATE
MAX9152 toc03
650 NC/RSEL = LOW OR OPEN
40
550
38 SUPPLY CURRENT (mA)
450 NC/RSEL = HIGH 350
36
34
250
32
150 CONDITIONS: 3.3V, PRBS = 223 -1 DATA PATTERN, |VID| = 200mV, VCM = +1.2V HORIZONTAL SCALE = 200ps/div VERTICAL SCALE = 100mV/div 50 75 100 125 150 175 200 LOAD RESISTOR ()
30 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
4
_______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID = 200mV, PRBS = 223 - 1 data pattern, VCM = +1.2V, TA = +25C, unless otherwise noted.)
PEAK-TO-PEAK OUTPUT JITTER AT VCM = VID/2 vs. DATA RATE
MAX9152 toc04
MAX9152
PEAK-TO-PEAK OUTPUT JITTER AT VCM = +1.2V vs. DATA RATE
MAX9152 toc05
PEAK-TO-PEAK OUTPUT JITTER AT VCM = +3.3V - (VID/2) vs. DATA RATE
MAX9152 toc06
80
80
90 80 PEAK-TO-PEAK JITTER (ps) 70 60 50 40 VID = 0.8V VID = 0.2V
PEAK-TO-PEAK JITTER (ps)
PEAK-TO-PEAK JITTER (ps)
70
70 VID = 0.2V 60
60 VID = 0.2V VID = 0.8V 40 VID = 0.4V 30 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
50
50 VID = 0.8V 40 VID = 0.4V 30 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
VID = 0.4V 30 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
PEAK-TO-PEAK OUTPUT JITTER AT VCM = +0.4V vs. DATA RATE
MAX9152 toc07
PEAK-TO-PEAK OUTPUT JITTER AT VCM = +1.6V vs. DATA RATE
MAX9152 toc08
80
80
PEAK-TO-PEAK JITTER (ps)
VID = 0.4V 60 VID = 0.2V 50
PEAK-TO-PEAK JITTER (ps)
70
70
60
VID = 0.8V VID = 0.4V
50
40 VID = 0.8V 30 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
40
VID = 0.2V
30 100 200 300 400 500 600 700 800 DATA RATE (Mbps)
_______________________________________________________________________________________
5
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
Pin Description
PIN 1, 2 3, 4 5 6, 7 8 9 10, 11 12 13, 14 NAME SEL1, SEL0 IN0+, IN0VCC IN1+, IN1NC/RSEL NC OUT1-, OUT1+ GND OUT0-, OUT0+ FUNCTION LVCMOS/LVTTL Logic Inputs. Allow the switch to be configured as a mux, repeater, or splitter. LVDS/LVPECL Differential Input 0 Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. LVDS/LVPECL Differential Input 1 Logic Input. Selects differential output resistance. Set NC/RSEL to open or low when RL = 75, set to high when RL = 100. No Connect LVDS Differential Output 1 Ground LVDS Differential Output 0 LVCMOS/LVTTL Logic Inputs. Enables or disables the outputs. Setting EN0 or EN1 high enables the corresponding output, OUT0 or OUT1. Setting EN0 or EN1 low puts the corresponding output into high impedance (differential output resistance is also high impedance).
15, 16
EN1, EN0
Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9152 is an 800Mbps 2 x 2 crosspoint switch designed for high-speed, low-power point-to-point and multidrop interfaces. The device accepts LVDS or differential LVPECL signals and routes them to outputs depending on the selected mode of operation. A differential input with a magnitude of 0.1V to VCC with single-ended voltage levels at or within the MAX9152's VCC and ground switches the output. A differential input with a magnitude of at least 0.15V with single-ended voltage levels at or within the MAX9152's VCC and ground is required to meet the AC specifications. In the 1:2 splitter mode, the outputs repeat the selected input. This is useful for distributing a signal or creating a copy for use in protection switching. In the repeater
6
1/2 MAX9152
OUT_+
RL/2 IN_+ VOS IN_RL/2 ENABLED VID = (VIN_+) - (VIN_-) OUT_VOD = VOD - VOD* VOS = VOS - VOS* VOD AND VOS ARE MEASURED WITH VID = +100mV. VOD* AND VOS* ARE MEASURED WITH VID = -100mV. VOD
Figure 1. Test Circuit for VOD and VOS
mode, the device operates as a two-channel buffer. Repeating restores signal amplitude, allowing isolation of media segments or longer media drive. The device is a crosspoint switch where any input can be connected to any output or outputs. In 2:1 mux mode, primary and backup signals can be selected to provide a protection-switched, fault-tolerant application.
_______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
IN0+ VID = 0 IN0IN1VID = 0 IN1+
1.5V SEL_ tSET OUT_+ IN0 OUT_EN0 = EN1 = HIGH VID = (VIN_+) - (VIN_-) tSWITCH IN1 tHOLD
Figure 2. Input to Rising Edge Select Setup, Hold, and Mux Switch Timing Diagram
IN0+ VID = 0 IN0IN1VID = 0 IN1+ SEL_ 1.5V tSET OUT_IN1 OUT_+ EN0 = EN1 = HIGH VID = (VIN_+) - (VIN_-) tSWITCH IN0 tHOLD
Figure 3. Input to Falling Edge Select Setup, Hold, and Mux Switch Timing Diagram
Input Fail-Safe
The differential inputs of the MAX9152 do not have internal fail-safe biasing. If fail-safe biasing is required, it can be implemented with external large-value resistors. IN_+ should be pulled up to VCC with 10k and IN_ should be pulled down to GND with 10k. The voltage-divider formed by the 10k resistors and the 100 termination resistor (across IN_+ and IN_-) provides a slight positive differential bias and sets a high state at the device output when inputs are undriven.
compared to a high-impedance output. A termination resistor at the receiver is still required and is the primary termination for the interconnect. Select the output resistance that best matches the differential characteristic impedance of the interconnect used.
Select Function
The SEL0 and SEL1 logic inputs allow the device to be configured as a high-speed differential crosspoint, 2:1 mux, 1:2 demux, dual repeater, or 1:2 splitter (Figure 8). See Table 1 for mode selection settings.
Output Resistance
The MAX9152 has a selectable differential output resistance to reduce reflections from impedance discontinuities in the interconnect. Reflections are reduced,
Enable Function
The EN0 and EN1 logic inputs enable and disable driver outputs OUT0 and OUT1. Setting EN0 or EN1 high enables the corresponding driver output. Setting EN0
7
_______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
or EN1 low puts the corresponding driver output into a high-impedance state (the differential output resistance also becomes high impedance).
Table 1. Input/Output Function Table
SEL0 L L H H SEL1 L H L H OUT0 IN0 IN0 IN1 IN1 OUT1 IN0 IN1 IN0 IN1 MODE 1:2 splitter Repeater Switch 1:2 splitter
OUT_+ CL IN_+ IN_PULSE GENERATOR EN_ 50 1/2 MAX9152 CL VID = (VIN_+)-(VIN_-) EN_ 1.5V VOUT_ + WHEN VID = +100mV VOUT_ - WHEN VID = -100mV tPHZ 50% 1.5V 0 tPZH VOH 50% 1.2V 1.2V VOUT_ + WHEN VID = -100mV VOUT_ - WHEN VID = +100mV 50% tPLZ tPZL 50% VOL 3V OUT_RL/2
RL/2
Applications Information
Unused Differential Inputs
+1.2V
Unused differential inputs should be tied to ground and VCC to prevent the high-speed input stage from switching due to noise. IN_+ should be pulled to VCC with 10k and IN_- should be pulled to GND with 10k.
Expanding the Number of LVDS Output Ports
Devices can be cascaded to make larger switches. Total propagation delay and total jitter should be considered to determine the maximum allowable switch size. Three MAX9152s are needed to make a 2 input x 4 output crosspoint switch with two device propagation delays. Seven MAX9152s make a 2 input x 8 output crosspoint with three device delays.
Accepting PECL Inputs
The inputs accept PECL signals with the use of an attenuation circuit, as shown in Figure 9.
Power-Supply Bypassing
Figure 4. Output Active to High-Z and High-Z to Active Test Circuit and Timing Diagram
Bypass VCC to ground with high-frequency surfacemount ceramic 0.1F and 0.001F capacitors in paral-
SEL0 IN0+ IN00 CL OUT0+ RL 1 PULSE GENERATOR 50 50
MAX9152
CL
OUT0-
CL 0
OUT1+ RL
IN1IN1+ ENABLED
1 SEL1
CL
OUT1-
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit 8 _______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
VIN_VID = 0 VIN_+ VOUT_VOD = 0 VOUT_+ 80% 50% 20% tLHT VID = (VIN_+) - (VIN_-) VOD = (VOUT_+) - (VOUT_-) tPLHD AND tPHLD ARE MEASURED FOR ANY COMBINATION OF SEL0 AND SEL1.
2:1 MUX IN1
VID = 0 tPHLD VOD = 0
IN1 OUT1 2 x 2 CROSSPOINT IN0 OUT0
tPLHD
80% 50% VOD = 0 20% tHLT
+VOD
VOD = 0
-VOD
IN0 OUT0 OR OUT1
Figure 6. Output Transition Time and Propagation Delay Timing Diagram
OUT0
VOUT0VOD = 0 VOUT0+ VOUT1VOD = 0 VOUT1+ VOD = (VOUT_+) - (VOUT_-) tCCS IS MEASURED WITH SEL0 = SEL1 = HIGH OR LOW (1:2 SPLITTER MODE) VOD = 0 tCCS VOD = 0 tCCS
IN0 OR IN1 OUT1
1:2 DEMUX
OUT0 IN0 OR IN1 OUT1
Figure 7. Output Channel-to-Channel Skew
lel as close to the device as possible, with the smaller value capacitor closest to VCC.
1:2 SPLITTER
Differential Traces
Trace characteristics affect the performance of the MAX9152. Use controlled-impedance traces. Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
IN0
OUT0
IN1 DUAL REPEATER
OUT1
Figure 8. Programmable Configurations
Cables and Connectors
Transmission media should have nominal differential impedance of 75 or 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the differential receiver.
Board Layout
For LVDS applications, a four-layer printed-circuit (PC) board that provides separate power, ground, and signal planes is recommended.
9
_______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
5V
Chip Information
TRANSISTOR COUNT: 880 PROCESS: CMOS
82 5V PECL 50 10k
82
3.3V 50 100 IN_+ IN_33 33 1/2 MAX9152
Figure 9. PECL to LVDS Level Conversion Network
Pin Configuration
TOP VIEW
SEL1 1 SEL0 2 INO+ 3 INO- 4 VCC 5 IN1+ 6 IN1- 7 NC/RSEL 8 16 EN0 15 EN1 14 OUT0+
MAX9152
13 OUT012 GND 11 OUT1+ 10 OUT19 NC
SO/TSSOP
10
______________________________________________________________________________________
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch
Package Information
TSSOP.EPS
MAX9152
______________________________________________________________________________________
11
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch MAX9152
Package Information (continued)
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9152

	To Download MAX9152 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .